1. Field of the Invention
This invention relates to the field of conductor layers for interconnection within microelectronics fabrications. More specifically, the invention relates to the field of damascene methods for forming interconnection layers within microelectronics fabrications.
2. Description of the Related Art
Microelectronics fabrications employ conductor layers formed into patterned lines to interconnect the devices from which the fabrications are made. As the dimensions of microelectronics fabrications have become smaller, the density of interconnections has increased and the requirements placed upon interconnections have become more stringent. The number and complexity of interconnections dictate that multiple levels of interconnections be employed in practical microelectronics fabrications. There has developed a need for multi-level interconnection wiring for microelectronics fabrications with increasing demands and constraints placed on materials and methods.
In order to avoid increased electrical resistance as dimensions and hence conductor cross-sectional areas decrease, the art of microelectronics fabrication has resorted to conductor materials having higher electrical conductivity, such as, for example, copper. In addition, methods to reduce electrical resistance at contact areas between interconnection levels and via contacts have been pursued. Finally, fabrication methods and materials for forming multi-level interconnection layers which afford surface planarity as the number of interconnection levels increases have been developed, since the patterning of conductor layers by subtractive etching of conductor layers formed over surfaces leads to resulting raised surface profiles of the patterned conductor layer, which may cause subsequent fabrication problems and lead to reliability concerns.
Methods and materials providing high density interconnections with low electrical resistance have been developed which are generally satisfactory for meeting the requirements of microelectronics fabrications. These include forming the interconnection layer patterns from copper metal because of its intrinsically high electrical conductivity. The copper lines may be formed within depressions or trenches within a dielectric layer employing the method of “damascene” or inlaid pattern formation to provide a co-planar surface of the inlaid copper line pattern and the surrounding dielectric layer. Such trench patterns are often etched into an inter-level metal dielectric (IMD) layer employing photolithographic methods including an etch stop layer formed over the underlying via contact hole filled with a conductor material “stud” or “plug” to form a damascene stacked conductor interconnection layer. Such, damascene stacked conductor interconnection layers are not without problems, however.
For example, the use of copper metal as the via contact hole fill or stud to form an integral damascene stacked conductor layer is not feasible at the first level of contact, to the semiconductor device itself, since copper acts as a deleterious material in semiconductor devices with degrading effect on device operation. Thus it is necessary to employ a different metal such as tungsten for the via contact hole stud. In forming contact between the overlying copper layer and the tungsten stud, there are difficulties with conventional chemical mechanical polish (CMP) planarization of the tungsten stud and subsequent formation and etching of an IMD layer in which the copper lines are to be inlaid. This is particularly true if the planarization of the tungsten stud by harsh chemical exposure removes or damages the etch stop layer needed for the trench etching.
It is therefore towards the goal of forming improved multi-level conductor layers employing damascene methods and various conductor materials that the present invention is more generally directed.
Various methods have been disclosed for formation of damascene interconnection conductor layers with etch stop layers within semiconductor microelectronics fabrications.
For example, Kano, in U.S. Pat. No. 5,380,679, discloses a method for forming a multi-level conductor wiring structure in a microelectronics fabrication affording improved adhesion between layers with no additional photolithographic steps. The method employs an intermediate bonding conductor layer to improve adhesion between the component sub-layers which form the main part of the multilevel conductor structure. The conductor layers are formed by electroplating.
Further, Woo et al., in U.S. Pat. No. 5,451,543, disclose a method for forming vertical sidewalls when etching via contact holes through intermediate dielectric layers over conductor lines and lands. The method employs an etch stop layer which prevents resputtering which tends to form non-vertical sidewall profiles.
Finally, Cronin, in U.S. Pat. No. 5,818,110, discloses a method for forming multi-layer dual damascene interconnection layers without requiring interlock vias. The method employs etched via contact hole at locations such that wide and narrow openings are available. When refilled with a conformal deposited conductor layer of appropriate thickness, the narrow openings are completely gap filled, while the wide openings are only partially filled with central openings. Subsequent CMP planarization leaves the narrow holes filled with a conductor plug to the next conductor level, while the wide holes are non-conductor filled and not available for next-level interconnection.
Desirable in the art of microelectronics fabrication are additional methods for fabrication of improved multi-level conductor interconnection structures wherein there is formed a low resistance, high strength bond between the via hole contact conductor plug and the inlaid conductor wiring layer. Also desirable are damascene methods of formation whereby the underlying conductor plug and etch stop layer experiences limited damage during formation of the damascene structure.
It is towards these goals that the present invention is generally directed.